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| VGA Port Companion Circuit PACVGA105 Features * Seven channels of ESD protection designed to meet IEC-1000-4-2 Level-4 ESD requirements (8kV contact discharge) Very low loading capacitance from ESD protection diodes at less than 5pF typical TTL to CMOS level-translating buffers for the HSYNC and VSYNC lines Three independent supply pins (VCC, VRGB and VAUX) to facilitate operation with sub-micron Graphics Controller ICs High impedance pull-ups (50k nominal to VAUX) for HSYNC and VSYNC inputs Pull-up resistors (1.8k nominal to VCC) for DDC_CLK and DDC_DATA lines Compact 16-pin QSOP package Lead-free version available Product Description The PACVGA105 incorporates 7 channels of ESD protection for signal lines commonly found in a VGA port for PCs. ESD protection is implemented with current steering diodes designed to safely handle the high peak surge currents associated with the IEC1000-4-2 Level-4 ESD Protection Standard (8kV contact discharge). When the channels are subjected to an electrostatic discharge, the ESD current pulse is diverted via the protection diodes into the positive supply rails or ground where they may be safely dissipated. The upper ESD diodes for the R, G and B channels are connected to a separate supply rail (VRGB) to facilitate interfacing to graphics controller ICs with low voltage supplies. The remaining channels are connected to the main 5V rail (VCC). The lower diodes for the R, G and B channels are also connected to a dedicated ground pin (GNDA) to minimize crosstalk due to common ground impedance. Two non-inverting buffers are also included in this IC for buffering the HSYNC and VSYNC signals from the graphics controller IC. These buffers will accept TTL input levels and convert them to CMOS output levels that swing between GND and VCC. These drivers have a nominal 60 output impedance to match the characteristic impedance of the HSYNC and VSYNC lines of the video cables typically used. The inputs of these drivers also have high impedance pull-ups (50kW nom.) pulling up to the VAUX rail. In addition, the DDC_CLOCK and DDC_DATA channels have 1.8k resistors pulling these inputs up to the main 5V (VCC) rail. * * * * * * * Applications * * * * ESD protection and termination resistors for VGA (video) port interfaces Desktop PCs Notebook computers LCD monitors (c)2010 SCILLC. All rights reserved. May 2010 Rev. 2 Publication Order Number: PACVGA105/D PACVGA105 Simplified Electrical Schematic VRGB VCC VAU X 1.8k 1.8k 50k 50k R G B DDC_CLK VSYNC_OUT GNDA DDC_DA TA HSYNC VSYNC GNDD HSYNC_OUT Rev. 2 | Page 2 of 9 | www.onsemi.com PACVGA105 PIN DESCRIPTIONS LEAD(s) 1 NAME HSYNC_OUT DESCRIPTION Horizontal sync signal buffer output. Connects to the video connector side of the horizontal sync line. Horizontal sync signal buffer input. Connects to the VGA Controller side of the horizontal sync line. Digital ground reference supply pin. VRGB supply pin. This is an isolated supply pin for the R, G and B ESD protection circuits. Blue signal video protection channel. This pin is typically tied to the B video line between the VGA controller device and the video connector. Green signal video protection channel. This pin is typically tied to the G video line between the VGA controller device and the video connector. Red signal video protection channel. This pin is typically tied to the R video line between the VGA controller device and the video connector. Analog ground reference supply pin. VCC supply pin. This is the main supply input for the DDC_CLK and DDC_DATA pullup resistors and ESD protection circuits. It is also connected to the sync buffers and to the ESD protection diodes present on the HSYNC_OUT and VSYNC_OUT lines. DDC data pin. DDC clock pin. VAUX supply pin. This is the supply input for the 50k pullups connected to the HSYNC and VSYNC buffer inputs. Vertical sync signal buffer input. Connects to the VGA Controller side of the vertical sync line. Vertical sync signal buffer output. Connects to the video connector side of the vertical sync line. 2 HSYNC 3, 11 4 5 GNDD VRGB B 6 G 7 R 8 9, 16 GNDA VCC 10 12 13 DDC_DATA DDC_CLK VAUX 14 15 VSYNC VSYNC_OUT Rev. 2 | Page 3 of 9 | www.onsemi.com PACVGA105 Ordering Information PART NUMBERING INFORMATION Standard Finish Pins Package Ordering Part Number1 PACVGA105Q Part Marking PACVGA105Q Lead-free Finish Ordering Part Number1 PACVGA105QR Part Marking PACVGA105QR 16 QSOP Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER VCC,VRGB,VAUX Supply Voltage Inputs Diode Forward Current (one diode conducting at a time) DC Voltage at Inputs R, G, B HSYNC, VSYNC DDC_CLK, DDC_DATA Operating Temperature Range Storage Temperature Range Package Power Rating RATING [GND - 0.5] to +6.0 20 UNITS V mA [GND - 0.5] to [VRGB + 0.5] [GND - 0.5] to [VAUX + 0.5] [GND - 0.5] to [VCC + 0.5] 0 to +70 -40 to +150 750 V V V C C mW Rev. 2 | Page 4 of 9 | www.onsemi.com PACVGA105 STANDARD OPERATING CONDITIONS SYMBOL VCC VRGB VAUX VIH VIL VI PARAMETER Main Supply Voltage RGB Supply Voltage Auxiliary Supply Voltage Logic High Input Voltage (Note 1) Logic Low Input Voltage (Note 1) Input Voltage RGB HSYNC, VSYNC DDC_CLK, DDC_DATA High Level Output Current (Note 1) Low Level Output Current (Note 1) Free-air Operating Temperature Note 1: These parameters apply only to the HSYNC and VSYNC signals. MIN 4.5 1.7 2.9 2.0 MAX 5.5 3.7 3.7 UNITS V V V V 0.8 V 0 0 0 VRGB VAUX VCC -8 8 V V V mA mA C IOH IOL TA 0 +70 Rev. 2 | Page 5 of 9 | www.onsemi.com PACVGA105 ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL VF VOH VOL IIN PARAMETER Diode Forward Voltage Logic High Output Voltage Logic Low Output Voltage Input Current R, G and B pins HSYNC, VSYNC pins HSYNC, VSYNC pins VCC Supply Current CONDITIONS IF = 10mA IOH = -4mA, VCC = 4.5V IOL = 4mA, VCC = 4.5V VRGB = 3.63V, VIN = VRGB or GND VAUX = 3.63V, VIN = VAUX VAUX = 3.63V, VIN = GND VCC = 5.5V; VAUX = VRGB = 2.97V; All inputs and outputs floating R, G and B pins at VCC or GND; All inputs and outputs floating Note 2 applies for all cases 5 10 5 pF pF pF 4.0 0.4 MIN TYP MAX 1.0 UNITS V V V A A A A -30 -72.5 35 +1 +1 -95 100 ICC IRGB VRGB Supply Current 10 A CIN Input Capacitance R, G and B pins HSYNC, VSYNC pins DDC_DATA, DDC_CLK pins Pull-up Resistance DDC_DATA, DDC_CLK pins ESD Withstand Voltage RPU VESD 1.62 VCC = 5V; VRGB = 3.3V; VAUX = 3.3V; Note 3 CL = 50pF; VCC = 5.0V; RL = 500; Note 4 CL = 50pF; VCC = 5.0V; RL = 500; Note 4 CL = 50pF; VCC = 5.0V; RL = 500; Note 4 8 1.8 1.98 k kV tPLH SYNC Buffer L => H Propagation Delay SYNC Buffer H => L Propagation Delay SYNC Buffer Output Rise & Fall Times 7.0 15.0 ns tPHL 7.0 15.0 ns tR, tF 7.0 ns Note 1: All parameters specified over standard operating conditions unless otherwise noted. Note 2: Measured at 1MHz. R/G/B inputs biased at 1.65V with VRGB = 3.3V. DDC_CLK and DDC_DATA biased at 2.5V with VCC=5V. HSYNC and VSYNC inputs biased at VAUX or GND with VAUX = 3.3V and VCC = 5V. Note 3: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. VRGB and VCC must be bypassed to GND via a low impedance ground plane with a 0.2uF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: R, G, B, HSYNC_OUT, VSYNC_OUT, DDC_CLK and DDC_DATA. The HSYNC and VSYNC inputs are ESD protected to the industry standard 2kV per the Human Body Model (MIL-STD-883, Method 3015). Note 4: Applicable to the SYNC buffers only. Input signals swing between 0V and 3.0V, with rise and fall times 5ns. Guaranteed by correlation to buffer output drive currents. Rev. 2 | Page 6 of 9 | www.onsemi.com PACVGA105 Application Information Figure 1. Typical Connection Diagram GNDA, the negative voltage rail for the R, G and B diodes is not connected internally to GNDD. GNDA should ideally be connected to the ground of the video DAC IC. This will prevent any ground bounce caused by digital signals from injecting noise onto the R, G and B signals. Analog GND and digital GND are typically connected on the printed circuit board. Rev. 2 | Page 7 of 9 | www.onsemi.com PACVGA105 Mechanical Details QSOP Mechanical Specifications PACVGA105 devices are packaged in 16-pin QSOP packages. Dimensions are presented below. For complete information on the QSOP-16 package, see the California Micro Devices QSOP Package Information document. PACKAGE DIMENSIONS Package Pins Millimeters Dimensions Min A A1 B C D E e H L # per tube # per tape and reel 1.35 0.10 0.20 0.18 4.80 3.81 Max 1.75 0.25 0.30 0.25 5.00 3.98 Min 0.053 0.004 0.008 0.007 0.189 0.150 Max 0.069 0.010 0.012 0.010 0.197 0.157 QSOP (JEDEC name is SSOP) 16 Inches 0.64 BSC 5.79 0.40 6.19 1.27 0.025 BSC 0.228 0.016 0.244 0.050 100 pcs* 2500 pcs Controlling dimension: inches Package Dimensions for QSOP-16 * This is an approximate number which may vary. Rev. 2 | Page 8 of 9 | www.onsemi.com PACVGA105 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative Rev. 2 | Page 9 of 9 | www.onsemi.com |
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